SH7203 Datasheet, PDF (1150/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 USB 2.0 Host/Function Module (USB)
23.3.12 Interrupt Enabled Register 1 (INTENB1)
INTENB1 is a register that specifies the masking of various interrupts and controls the BRDY
interrupt status clear timing.
This register is initialized by a power-on reset. By a software reset, bits other than BRDYM are
initialized.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
- BCHGE - DTCHE -
-
-
-
-
- SIGNE SACKE - BRDYM -
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R/W R R/W R
R
R
R
R
R R/W R/W R R/W R
R
Initial
Bit
Bit Name
Value R/W Description
15
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
14
BCHGE
0
R/W USB Bus Change Interrupt Enable
0: Interrupt output disabled
1: Interrupt output enabled
13
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
12
DTCHE
0
R/W Disconnection Detection Interrupt Enable during Full-
Speed Operation
The disconnection detection using this bit is valid
only when the host controller function is selected and
full-speed operation is performed. During high-speed
operation, software should be used to detect
disconnection by detecting no response from a
function or by another appropriate method.
0: Interrupt output disabled
1: Interrupt output enabled
Note:
When high-speed operation established
(RHST = 11) is determined after a reset
handshake, keep DTCHE cleared to 0 during
high-speed communication.
Rev. 2.00 Apr. 16, 2008 Page 1120 of 1652
REJ09B0313-0200