SH7203 Datasheet, PDF (1367/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 25 Pin Function Controller (PFC)
Bit
3
2 to 0
Bit Name
⎯
Initial
Value
0
PE0MD[2:0] 000
R/W Description
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R/W PE0 Mode
Select the function of the PE0/BS/RxD0/ADTRG pin.
000: PE0 I/O (port)
001: BS output (BSC)
010: Setting prohibited
011: RxD0 input (SCIF)
100: ADTRG input (ADC)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
25.2.9 Port F I/O Registers H, L (PFIORH, PFIORL)
PFIORH and PFIORL are 16-bit readable/writable registers that are used to set the pins on port F
as inputs or outputs. The PF30IOR to PF0IOR bits correspond to the PF30/AUDIO_CLK to
PF0/TCLKA/LCD_DATA0/SSCK0 pins, respectively. PFIORH and PFIORL are enabled when
the port F pins are functioning as general-purpose inputs/outputs (PF30 to PF0). In other states,
they are disabled. If a bit in PFIORH/PFIORL is set to 1, the corresponding pin on port F
functions as an output. If it is cleared to 0, the corresponding pin functions as an input.
Bit 15 of PFIORH is reserved. This bit is always read as 0. The write value should always be 0.
(1) Port F I/O Register H
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
PF30 PF29 PF28 PF27 PF26 PF25 PF24 PF23 PF22 PF21 PF20 PF19 PF18 PF17 PF16
IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 2.00 Apr. 16, 2008 Page 1337 of 1652
REJ09B0313-0200