SH7203 Datasheet, PDF (328/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 9 Bus State Controller (BSC)
CKIO
T1
T2
T1
T2
A25 to A0
CSn
RD/WR
Read
Write
RD
D15 to D0
WEn
D15 to D0
BS
DACKn ^*
WAIT
Note: * The waveform for DACKn is when active low is specified.
Figure 9.4 Continuous Access for Normal Space 2
Bus Width = 16 Bits, Longword Access, CSnWCR.WM Bit = 1
(Access Wait = 0, Cycle Wait = 0)
Rev. 2.00 Apr. 16, 2008 Page 298 of 1652
REJ09B0313-0200