SH7203 Datasheet, PDF (387/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 9 Bus State Controller (BSC)
Th
T1
Tw
T2
Tf
CKIO
A25 to A0
CSn
WEn
RD/WR
Read
RD
D31 to D0
RD/WR
Write
RD
D31 to D0
High
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 9.38 Wait Timing for SRAM with Byte Selection (BAS = 1)
(SW[1:0] = 01, WR[3:0] = 0001, HW[1:0] = 01)
Rev. 2.00 Apr. 16, 2008 Page 357 of 1652
REJ09B0313-0200