SH7203 Datasheet, PDF (147/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 5 Exception Handling
Section 5 Exception Handling
5.1 Overview
5.1.1 Types of Exception Handling and Priority
Exception handling is started by sources, such as resets, address errors, register bank errors,
interrupts, and instructions. Table 5.1 shows their priorities. When several exception handling
sources occur at once, they are processed according to the priority shown.
Table 5.1 Types of Exception Handling and Priority Order
Type
Exception Handling
Reset
Power-on reset
Manual reset
Address
error
CPU address error
DMAC address error
Instruction Integer division exception (division by zero)
Integer division exception (overflow)
Register Bank underflow
bank error _{Bank overflow}
Interrupt NMI
User break
H-UDI
IRQ
PINT
On-chip peripheral modules Direct memory access controller (DMAC)
USB2.0 host/function module (USB)
LCD controller (LCDC)
Compare match timer (CMT)
Bus state controller (BSC)
Watchdog timer (WDT)
Multi-function timer pulse unit 2 (MTU2)
A/D converter (ADC)
Priority
High
Low
Rev. 2.00 Apr. 16, 2008 Page 117 of 1652
REJ09B0313-0200