SH7203 Datasheet, PDF (1590/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 31 Electrical Characteristics
CKIO
A25 to A0
A12/A11^*1
Tr
Tc
Td1
Tde
Tap
Tr
Tc
Tnop
Trw1
Tap
t_AD3
t_AD3
t_AD3
Row
address
Column
address
t_AD3
t_AD3
t_AD3
READA
Command
t_AD3
t_AD3
Row
address
t_AD3
Column
address
t_AD3
t_AD3
t_AD3
t_AD3
WRITA
Command
CSn
RD/WR
RASU/L
CASU/L
tCSD2
tCSD2
t_RWD2
tRASD2
tRASD2
t_CASD2
t_CASD2
t_CASD2
tCSD2
tCSD2
t_RWD2
t_RWD2
tRASD2
tRASD2
t_CASD2
t_CASD2
DQMxx
D31 to D0
BS
tDQMD2
tDQMD2
t_RDH4
t_RDS4
t_BSD
t_BSD
tDQMD2
tDQMD2
t_WDD3
t_WDH3
t_BSD
t_BSD
CKE
DACKn
TENDn *²
tDACD
(High)
tDACD
tDACD
(High)
tDACD
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Figure 31.39 Synchronous DRAM Access Timing in Low-Frequency Mode
(Auto-Precharge, TRWL = 2 Cycles)
Rev. 2.00 Apr. 16, 2008 Page 1560 of 1652
REJ09B0313-0200