SH7203 Datasheet, PDF (20/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

16.4.1 Transfer Clock ...................................................................................................... 800
16.4.2 Relationship of Clock Phase, Polarity, and Data .................................................. 800
16.4.3 Relationship between Data Input/Output Pins and Shift Register ........................ 801
16.4.4 Communication Modes and Pin Functions ........................................................... 803
16.4.5 SSU Mode............................................................................................................. 805
16.4.6 SCS Pin Control and Conflict Error...................................................................... 814
16.4.7 Clock Synchronous Communication Mode .......................................................... 815
16.5 SSU Interrupt Sources and DMAC .................................................................................... 822
16.6 Usage Note......................................................................................................................... 823
16.6.1 Module Standby Mode Setting ............................................................................. 823
16.6.2 Note on Continuous Transmission/Reception in SSU Slave Mode ...................... 823
Section 17 I²C Bus Interface 3 (IIC3)................................................................ 825
17.1 Features.............................................................................................................................. 825
17.2 Input/Output Pins............................................................................................................... 827
17.3 Register Descriptions ......................................................................................................... 828
17.3.1 I²C Bus Control Register 1 (ICCR1)..................................................................... 829
17.3.2 I²C Bus Control Register 2 (ICCR2)..................................................................... 832
17.3.3 I²C Bus Mode Register (ICMR)............................................................................ 834
17.3.4 I²C Bus Interrupt Enable Register (ICIER) ........................................................... 836
17.3.5 I²C Bus Status Register (ICSR)............................................................................. 838
17.3.6 Slave Address Register (SAR).............................................................................. 841
17.3.7 I²C Bus Transmit Data Register (ICDRT) ............................................................ 841
17.3.8 I²C Bus Receive Data Register (ICDRR).............................................................. 842
17.3.9 I²C Bus Shift Register (ICDRS)............................................................................ 842
17.3.10 NF2CYC Register (NF2CYC) .............................................................................. 843
17.4 Operation ........................................................................................................................... 844
17.4.1 I²C Bus Format...................................................................................................... 844
17.4.2 Master Transmit Operation ................................................................................... 845
17.4.3 Master Receive Operation .................................................................................... 847
17.4.4 Slave Transmit Operation ..................................................................................... 849
17.4.5 Slave Receive Operation....................................................................................... 852
17.4.6 Clocked Synchronous Serial Format..................................................................... 853
17.4.7 Noise Filter ........................................................................................................... 857
17.4.8 Example of Use..................................................................................................... 858
17.5 Interrupt Requests .............................................................................................................. 862
17.6 Bit Synchronous Circuit..................................................................................................... 863
17.7 Usage Notes ....................................................................................................................... 864
17.7.1 Note on the Setting of ICCR1.CKS[3:0] .............................................................. 864
17.7.2 Settings for Multi-Master Operation..................................................................... 864
Rev. 2.00 Apr. 16, 2008 Page xx of xxx
REJ09B0313-0200