SH7203 Datasheet, PDF (1437/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 28 Power-Down Modes
Bit
6 to 4
3
2
1
0
Bit Name
⎯
Initial
Value
All 0
SSI3SRST 0
SSI2SRST 0
SSI1SRST 0
SSI0SRST 0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W SSI3 Software Reset
Controls the SSI3 reset by software
0: Cancels the SSI3 reset.
1: Puts the SSI3 in the reset state.
R/W SSI2 Software Reset
Controls the SSI2 reset by software
0: Cancels the SSI2 reset.
1: Puts the SSI2 in the reset state.
R/W SSI1 Software Reset
Controls the SSI1 reset by software
0: Cancels the SSI1 reset.
1: Puts the SSI1 in the reset state.
R/W SSI0 Software Reset
Controls the SSI0 reset by software
0: Cancels the SSI0 reset.
1: Puts the SSI0 in the reset state.
Rev. 2.00 Apr. 16, 2008 Page 1407 of 1652
REJ09B0313-0200