SH7203 Datasheet, PDF (1452/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 28 Power-Down Modes
To ensure that data is actually
retained by the on-chip RAM
(for data retention), set H'09 to
DSRTR
Set the RRAMKP bit in DSCTR
as needed
Transfer data that needs to be
retained to the corresponding
area
Set the corresponding bit in
DSSSR as needed
Set the registers of the INTC
as needed
Perform read/write to the same
arbitrary address in each
retention page of the on-chip
RAM (for data retention)
Set the STBY and DEEP bits
in STBCR to 1
Read STBCR
Clear the flags of DSFR
Execute the SLEEP instruction
Transition to deep standby mode
Figure 28.2 Flowchart of Transition to Deep Standby Mode
Rev. 2.00 Apr. 16, 2008 Page 1422 of 1652
REJ09B0313-0200