SH7203 Datasheet, PDF (1069/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 21 D/A Converter (DAC)
21.3 Register Descriptions
The D/A converter has the following registers.
Table 21.2 Register Configuration
Register Name
D/A data register 0
D/A data register 1
D/A control register
Abbreviation R/W
DADR0
R/W
DADR1
R/W
DACR
R/W
Initial
Value
H'00
H'00
H'1F
Address
H'FFFE6800
H'FFFE6801
H'FFFE6802
Access
Size
8, 16
8, 16
8, 16
21.3.1 D/A Data Registers 0 and 1 (DADR0 and DADR1)
DADR is an 8-bit readable/writable register that stores data to which D/A conversion is to be
performed. Whenever analog output is enabled, the values in DADR are converted and output to
the analog output pins.
DADR is initialized to H'00 by a power-on reset or in module standby mode.
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 2.00 Apr. 16, 2008 Page 1039 of 1652
REJ09B0313-0200