SH7203 Datasheet, PDF (40/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 1 Overview
1.3 Block Diagram
SH-2A
CPU core
Floating-point
unit (FPU)
CPU instruction fetch bus (F bus)
CPU bus
(C bus)
CPU memory access bus (M bus) _{(I clock)}
Cache
controller
Instruction
cache memory
8 Kbytes
Operand
cache memory
8 Kbytes
On-chip RAM
(high-speed)
64 Kbytes
Internal LCD bus
(IL bus)
LCD I/F I/O
LCD
controller
(LCDC)
Bus state
controller
(BSC)
USB2.0 host/
function module
(USB)
Port
External bus I/O
External bus width
mode input
Port
USB bus I/O
USB clock input
User break
controller
(UBC)
UBCTRG output
Internal CPU bus
(IC bus)
Internal DMA bus
(ID bus)
Internal bus
(I bus)
(B clock)
Peripheral
bus controller
Direct memory
access
controller
(DMAC)
DREQ input
DACK output
TEND output
Peripheral bus (P clock)
Pin function
controller
(PFC)
I/O ports
Clock pulse
generator
(CPG)
Interrupt
controller
(INTC)
Multi-function
timer pulse
unit 2
(MTU2)
Compare
match
timer
(CMT)
Watchdog
timer
(WDT)
Realtime
clock
(RTC)
Serial
communication
interface with FIFO
(SCIF)
Synchronous
serial commnication
unit
(SSU)
Port
General I/O
Port
Port
Port
EXTAL input
XTAL output
CKIO I/O
Clock mode input
RES input
MRES input
MMI input
IRQ input
PINT input
IRQOUT output
Timer pulse I/O
Port
Port
WDTOVF RTC_X1 input
output RTC_X2 output
Port
Serial I/O
Port
Serial I/O
User
debugging
interface
(H-UDI)
Power-down
mode
control
On-chip RAM
(retention)
16 Kbytes
AND/NAND
flash memory
controller
(FLCTL)
D/A converter
(DAC)
A/D converter
(ADC)
Controller
area
network
(RCAN-TL1)
Serial
sound
interface
(SSI)
I²C bus
interface 3
(IIC3)
Port
JTAG I/O
Port
Flash memory
I/F I/O
Port
Analog output
Port
Analog input
ADTRG input
Port
CAN bus I/O
Port
Serial I/O
Audio clock input
Port
I²C bus I/O
Figure 1.1 Block Diagram
Rev. 2.00 Apr. 16, 2008 Page 10 of 1652
REJ09B0313-0200