SH7203 Datasheet, PDF (1095/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 22 AND/NAND Flash Memory Controller (FLCTL)
Initial
Bit
Bit Name Value R/W Description
19
AC1CLR 0
R/W FLECFIFO Clear
Clears FLECFIFO. When changing the read/write
direction, clear the FIFO.
0: Retains the FLECFIFO value. In flash-memory
access, this bit should be cleared to 0.
1: Clears FLECFIFO. After FLECFIFO has been
cleared, this bit should be cleared to 0.
18
AC0CLR 0
R/W FLDTFIFO Clear
Clears FLDTFIFO. When changing the read/write
direction, clear the FIFO.
0: Retains the FLDTFIFO value. In flash-memory
access, this bit should be cleared to 0.
1: Clears FLDTFIFO. After FLDTFIFO has been
cleared, this bit should be cleared to 0.
17
DREQ1EN 0
R/W FLECFIFODMA Request Enable
Enables or disables the DMA transfer request issued
from FLECFIFO.
0: Disables the DMA transfer request issued from
FLECFIFO
1: Enables the DMA transfer request issued from
FLECFIFO
16
DREQ0EN 0
R/W FLDTFIFODMA Request Enable
Enables or disables the DMA transfer request issued
from FLDTFIFO.
0: Disables the DMA transfer request issued from the
FLDTFIFO
1: Enables the DMA transfer request issued from the
FLDTFIFO
15 to 10 —
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 2.00 Apr. 16, 2008 Page 1065 of 1652
REJ09B0313-0200