SH7203 Datasheet, PDF (817/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 16 Synchronous Serial Communication Unit (SSU)
Channel Register Name
1
SS receive data register 1_1
SS receive data register 2_1
SS receive data register 3_1
Abbreviation R/W
SSRDR1_1 R
SSRDR2_1 R
SSRDR3_1 R
Initial
value
H'00
H'00
H'00
Address
H'FFFE780B
H'FFFE780C
H'FFFE780D
Access
size
8
8, 16
8
16.3.1 SS Control Register H (SSCRH)
SSCRH specifies master/slave device selection, bidirectional mode enable, SSO pin output value
selection, SSCK pin selection, and SCS pin selection.
Bit: 7
6
5
4
3
2
1
0
MSS BIDE
-
SOL SOLP -
CSS[1:0]
Initial value: 0
0
0
0
1
1
0
1
R/W: R/W R/W R R/W R/W R R/W R/W
Initial
Bit
Bit Name Value R/W
7
MSS
0
R/W
6
BIDE
0
R/W
Description
Master/Slave Device Select
Selects that this module is used in master mode or
slave mode. When master mode is selected, transfer
clocks are output from the SSCK pin. When the CE bit
in SSSR is set, this bit is automatically cleared.
0: Slave mode is selected.
1: Master mode is selected.
Bidirectional Mode Enable
Selects that both serial data input pin and output pin are
used or one of them is used. However, transmission
and reception are not performed simultaneously when
bidirectional mode is selected. For details, section
16.4.3, Relationship between Data Input/Output Pins
and Shift Register.
0: Standard mode (two pins are used for data input and
output)
1: Bidirectional mode (one pin is used for data input and
output)
Rev. 2.00 Apr. 16, 2008 Page 787 of 1652
REJ09B0313-0200