SH7203 Datasheet, PDF (634/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(3) TCFV Flag/TCFU Flag Setting Timing
Figure 11.94 shows the timing for setting of the TCFV flag in TSR on overflow, and TCIV
interrupt request signal timing.
Figure 11.95 shows the timing for setting of the TCFU flag in TSR on underflow, and TCIU
interrupt request signal timing.
Pφ
TCNT input
clock
TCNT
(overflow)
Overflow
signal
TCFV flag
H'FFFF
H'0000
TCIV interrupt
Figure 11.94 TCIV Interrupt Setting Timing
Pφ
TCNT
input clock
TCNT
(underflow)
Underflow
signal
TCFU flag
H'0000
H'FFFF
TCIU interrupt
Figure 11.95 TCIU Interrupt Setting Timing
Rev. 2.00 Apr. 16, 2008 Page 604 of 1652
REJ09B0313-0200