SH7203 Datasheet, PDF (1671/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Main Revisions for this Edition
Item
Page
31.4.3 Bus Timing
1534
Figure 31.13 Basic Bus
Timing for Normal Space
(No Wait)
Figure 31.14 Basic Bus 1535
Timing for Normal Space
(One Software Wait
Cycle)
Figure 31.15 Basic Bus 1536
Timing for Normal Space
(One External Wait
Cycle)
Figure 31.16 Basic Bus 1537
Timing for Normal Space
(One Software Wait
Cycle, External Wait
Cycle Valid (WM Bit = 0),
No Idle Cycle)
Figure 31.17 MPX-I/O 1538
Interface Bus Cycle
(Three Address Cycles,
One Software Wait
Cycle, One External Wait
Cycle)
Revision (See Manual for Details)
Figure amended
CSn
Figure amended
t_CSD1
tCS
CSn
t_CSD1
t_CS
Figure amended
CSn
t_CSD1
t_CS
Figure amended
t_CSD1
CSn
t_CS
t_CSD1
t_CSD1
t_CS
Figure amended
AH
t_AHD
t_AHD
t_AHD
Read
RD
D15 to D0
WE1, WE0
Write
D15 to D0
t_RSD
t_MAD
t_AWH
Address
t_MAH
t_WED1
t_MAD
t_WDD1
t_MAH
t_AWH
Address
t_CSD1
t_CSD1
t_CSD1
t_CSD1
Data
t_RSD
t_RDH1
t_RDS1
Data
t_WED1
t_WDH4
t_WDH1
Rev. 2.00 Apr. 16, 2008 Page 1641 of 1652
REJ09B0313-0200