SH7203 Datasheet, PDF (1225/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 USB 2.0 Host/Function Module (USB)
(2) FIFO Port Functions
Table 23.19 shows the settings for the FIFO port functions of this module. In write access, writing
data until the buffer is full (or the maximum packet size for non-continuous transfers)
automatically enables sending of the data. To enable sending of data before the buffer is full (or
before the maximum packet size for non-continuous transfers), the BVAL bit in C/DnFIFOCTR
must be set to end the writing. Also, to send a zero-length packet, the BCLR bit in the same
register must be used to clear the buffer and then the BVAL bit set in order to end the writing.
In read access, reception of new packets is automatically enabled if all of the data has been read.
Data cannot be read when a zero-length packet is being received (DTLN = 0), so the BCLR bit in
the register must be used to release the buffer. The length of the data being received can be
confirmed using the DTLN bit in C/DnFIFOCTR.
Table 23.19 FIFO Port Function Settings
Register Name
Bit Name Function
Note
C/DnFIFOSEL
REW
Buffer memory rewind (re-read, rewrite
DCLRM
Automatically clears data received for For DnFIFO only
a specified pipe after the data has
been read
DREQE
Asserts DREQ signal
For DnFIFO only
MBW
FIFO port access bit width
TRENB
Enables transaction counter operation For DnFIFO only
TRCLR
Clears the current number of
transactions
For DnFIFO only
DEZPM
zero-length packet addition mode
For DMA only
ISEL
FIFO port access direction
For DCP only
C/DnFIFOCTR
BVAL
Ends writing to the buffer memory
BCLR*
Clears the buffer memory on the CPU
side
DTLN
Confirms the length of received data
DnFIFOTRN
TRNCNT Sets the received transaction count For DnFIFO only
CFIFOSIE (except
DCP)
TGL
SCLR
CPU/SIE buffer toggle
Clears the buffer memory on the SIE
side
For CFIFO only
For CFIFO only
Note: * When CFIFOSEL.CURPIPE = DCP, setting CFIFOCTR.BCLR to 1 also clears the
buffer memory on the SIE side.
Rev. 2.00 Apr. 16, 2008 Page 1195 of 1652
REJ09B0313-0200