SH7203 Datasheet, PDF (254/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 8 Cache
Operations in sections 8.3.2 to 8.3.5 are summarized in table 8.8.
Table 8.8 Cache Operations
Cache
Hit/
CPU Cycle miss
Write-back mode/
write through
U
mode
Bit
External Memory
Accession
(through internal bus)
Cache Contents
Instruction Instruction Hit
⎯
cache
fetch
⎯ Not generated
Not renewed
Miss ⎯
⎯ Cache renewal cycle is
generated
Renewed to new values by
cache renewal cycle
Operand
cache
Prefetch/ Hit
read
Either mode is
available
x Not generated
Not renewed
Miss
Write-through
mode
⎯ Cache renewal cycle is
generated
Renewed to new values by
cache renewal cycle
Write-back mode 0
Cache renewal cycle is
generated
Renewed to new values by
cache renewal cycle
1 Cache renewal cycle is
Renewed to new values by
generated. Then write-back cache renewal cycle
cycle in write-back buffer is
generated.
Write
Hit
Write-through
⎯ Write cycle CPU issues is Renewed to new values by write
mode
generated.
cycle the CPU issues
Write-back mode x Not generated
Renewed to new values by write
cycle the CPU issues
Miss
Write-through
mode
⎯ Write cycle CPU issues is
generated.
Not renewed*
Write-back mode 0
Cache renewal cycle is
generated
Renewed to new values by
cache renewal cycle.
Subsequently renewed again to
new values in write cycle CPU
issues.
1 Cache renewal cycle is
Renewed to new values by
generated. Then write-back cache renewal cycle.
cycle in write-back buffer is Subsequently renewed again to
generated.
new values in write cycle CPU
issues.
[Legend]
x: Don't care.
Note: Cache renewal cycle: 16-byte read access, write-back cycle in write-back buffer: 16-byte
write access
* Neither LRU renewed. LRU is renewed in all other cases.
Rev. 2.00 Apr. 16, 2008 Page 224 of 1652
REJ09B0313-0200