SH7203 Datasheet, PDF (1673/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Index
Numerics
16-bit/32-bit displacement ........................ 51
A
A/D conversion time
(multi mode and scan mode)................. 1030
A/D conversion time (single mode)...... 1029
A/D conversion timing ......................... 1029
A/D converter (ADC) ........................... 1011
A/D converter activation......................... 593
A/D converter characteristics................ 1596
A/D converter start request delaying
function................................................... 586
Absolute address....................................... 51
Absolute address accessing....................... 51
Absolute maximum ratings................... 1513
AC characteristics................................. 1523
AC characteristics measurement
conditions.............................................. 1595
Access size and data alignment .............. 289
Access wait control................................. 301
ADC timing .......................................... 1579
Address array.................................. 212, 226
Address array read .................................. 226
Address errors......................................... 127
Address map ........................................... 236
Address multiplexing.............................. 312
Address spaces
of on-chip high-speed RAM ................. 1385
Address spaces
of on-chip RAM for data retention ....... 1385
Address-array write
(associative operation) ............................ 227
Address-array write
(non-associative operation)..................... 226
Addressing modes..................................... 52
Analog input pin ratings ....................... 1035
AND/NAND flash memory controller
(FLCTL)................................................ 1045
Arithmetic operation instructions.............. 71
Auto-refreshing ....................................... 339
Auto-request mode.................................. 416
B
Bank active ............................................. 332
Banked register and input/output
of banks................................................... 181
BCHG interrupt..................................... 1181
BEMP interrupt..................................... 1175
Bit manipulation instructions .................... 82
Bit synchronous circuit ........................... 863
Branch instructions ................................... 76
BRDY interrupt..................................... 1168
Break detection and processing............... 779
Break on data access cycle...................... 204
Break on instruction fetch cycle.............. 203
Buffer memory...................................... 1189
Bulk transfers ........................................ 1208
Burst mode .............................................. 430
Burst MPX-I/O interface......................... 366
Burst read ................................................ 324
Burst ROM (clocked asynchronous)
interface .................................................. 352
Burst ROM (clocked synchronous)
interface .................................................. 371
Burst write............................................... 329
Bus arbitration......................................... 379
Bus format for SSI module ..................... 884
Bus state controller (BSC) ...................... 231
Bus timing............................................. 1531
Bus-released state...................................... 85
C
Cache ...................................................... 211
Rev. 2.00 Apr. 16, 2008 Page 1643 of 1652
REJ09B0313-0200