SH7203 Datasheet, PDF (1399/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 I/O Ports
26.5.2 Port D Data Registers L (PDDRL)
PDDRL is a 16-bit readable/writable register that stores port D data. The PD15DR to PD0DR bits
correspond to the PD15/D31/PINT7/ADTRG/TIOC4D to PD0/D16/IRQ0/SSCK0/
DREQ2/TIOC0A pins, respectively.
When a pin function is general output, if a value is written to PDDRL, that value is output directly
from the pin, and if PDDRL is read, the register value is returned directly regardless of the pin
state.
When a pin function is general input, if PDDRL is read, the pin state, not the register value, is
returned directly. If a value is written to PDDRL, although that value is written into PDDRL, it
does not affect the pin state. Table 26.8 summarizes PDDRL read/write operation.
Bit: 15
PD15
DR
Initial value: 0
R/W: R/W
14
PD14
DR
0
R/W
13
PD13
DR
0
R/W
12
PD12
DR
0
R/W
11
PD11
DR
0
R/W
10
PD10
DR
0
R/W
9
PD9
DR
0
R/W
8
PD8
DR
0
R/W
7
PD7
DR
0
R/W
6
PD6
DR
0
R/W
5
PD5
DR
0
R/W
4
PD4
DR
0
R/W
3
PD3
DR
0
R/W
2
PD2
DR
0
R/W
1
PD1
DR
0
R/W
0
PD0
DR
0
R/W
Initial
Bit
Bit Name Value R/W Description
15
PD15DR 0
R/W See table 26.8.
14
PD14DR 0
R/W
13
PD13DR 0
R/W
12
PD12DR 0
R/W
11
PD11DR 0
R/W
10
PD10DR 0
R/W
9
PD9DR 0
R/W
8
PD8DR 0
R/W
7
PD7DR 0
R/W
6
PD6DR 0
R/W
5
PD5DR 0
R/W
4
PD4DR 0
R/W
3
PD3DR 0
R/W
2
PD2DR 0
R/W
1
PD1DR 0
R/W
0
PD0DR 0
R/W
Rev. 2.00 Apr. 16, 2008 Page 1369 of 1652
REJ09B0313-0200