SH7203 Datasheet, PDF (37/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 1 Overview
Items
Specification
AND/NAND flash
memory controller
(FLCTL)
• Direct-connected memory interface with AND-/NAND-type flash
memory
• Read/write in sectors
• Two types of transfer modes: Command access mode and sector
access mode (512-byte data + 16-byte management code: with ECC)
• Interrupt request and DMAC transfer request
• Supports flash memory requiring 5-byte addresses (2 Gbits and more)
USB2.0 host/function • Conforms to the Universal Serial Bus Specification Revision 2.0
module (USB)
• 480-Mbps and 12-Mbps transfer rates provided
• Can be used as function
• Software setting supported
• On-chip 8-Kbyte RAM as communication buffers
LCD controller (LCDC) •
•
•
•
From 16 × 1 to 1024 × 1024 dots supported
Supports 4/8/15/16-bpp color modes
Supports 1/2/4/6-bpp gray scale modes
TFT/DSTN/STN panels supported
• Signal polarity setting function
• 24-bit color pallet memory (16 of the 24 bits are valid; R:5/G:6/B:5)
• Unified graphics memory architecture
I/O ports
• 82 I/Os, 16 inputs, and 1 output
• Input or output can be selected for each bit
• Internal weak keeper circuit
A/D converter (ADC) • 10-bit resolution
• Eight input channels
• A/D conversion request by the external trigger or timer trigger
D/A converter (DAC) • 8-bit resolution
• Two output channels
User break controller • Two break channels
(UBC)
• Addresses, data values, type of access, and data size can all be set
as break conditions
User debugging
interface (H-UDI)
• E10A emulator support
• JTAG-standard pin assignment
Rev. 2.00 Apr. 16, 2008 Page 7 of 1652
REJ09B0313-0200