SH7203 Datasheet, PDF (1078/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 22 AND/NAND Flash Memory Controller (FLCTL)
Figure 22.1 shows a block diagram of the FLCTL.
DMAC
Peripheral bus
INTC
DMA transfer
requests
(2 lines)
32
Peripheral bus interface
32 32
32
Registers
32
Interrupt
requests
(4 lines)
FLCTL
State
machine
QTSEL
FCKSEL
FIFO
256 bytes
ECC
Transmission/
reception
control
×1, ×1/2,
×1/4
CPG
FCLK
Peripheral clock Pφ
8
8
8
Flash memory
interface
Note: FCLK is an operating clock for interface signals with flash memory.
The division ratio is specified by FLCMNCR.
8
Control signal
AND/NAND
flash memory
Figure 22.1 FLCTL Block Diagram
Rev. 2.00 Apr. 16, 2008 Page 1048 of 1652
REJ09B0313-0200