SH7203 Datasheet, PDF (431/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Direct Memory Access Controller (DMAC)
Initial
Bit
Bit Name Value R/W Description
7
DL
6
DS
0
R/W DREQ Level
0
R/W DREQ Edge Select
These bits specify the sampling method of the DREQ
pin input and the sampling level.
These bits are valid only in CHCR_0 to CHCR_3.
These bits are reserved in CHCR_4 to CHCR_7; they
are always read as 0 and the write value should
always be 0.
If the transfer request source is specified as an on-chip
peripheral module or if an auto-request is specified, the
specification by these bits is ignored.
00: DREQ detected in low level
01: DREQ detected at falling edge
10: DREQ detected in high level
11: DREQ detected at rising edge
5
TB
0
R/W Transfer Bus Mode
Specifies the bus mode when DMA transfers data.
Note that the burst mode must not be selected when
TC = 0.
0: Cycle steal mode
1: Burst mode
4, 3
TS[1:0]
00
R/W Transfer Size
These bits specify the size of data to be transferred.
Select the size of data to be transferred when the
source or destination is an on-chip peripheral module
register of which transfer size is specified.
00: Byte unit
01: Word unit (two bytes)
10: Longword unit (four bytes)
11: 16-byte (four longword) unit
Rev. 2.00 Apr. 16, 2008 Page 401 of 1652
REJ09B0313-0200