SH7203 Datasheet, PDF (158/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 5 Exception Handling
5.3.2 Address Error Exception Handling
When an address error occurs, the bus cycle in which the address error occurred ends.* When the
executing instruction then finishes, address error exception handling starts. The CPU operates as
follows:
1. The exception service routine start address which corresponds to the address error that
occurred is fetched from the exception handling vector table.
2. The status register (SR) is saved to the stack.
3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
instruction to be executed after the last executed instruction.
4. After jumping to the exception service routine start address fetched from the exception
handling vector table, program execution starts. The jump that occurs is not a delayed branch.
Note: * In the case of an address error caused by a data read or write, if the address error is
caused by an instruction fetch and the bus cycle in which the address error occurred has
not ended by the end of the above operation, the CPU restarts address error exception
handling before the bus cycle ends.
Rev. 2.00 Apr. 16, 2008 Page 128 of 1652
REJ09B0313-0200