SH7203 Datasheet, PDF (17/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

11.8.4 Overview of Initialization Procedures and Mode Transitions
in Case of Error during Operation, etc.................................................................. 624
Section 12 Compare Match Timer (CMT).........................................................655
12.1 Features.............................................................................................................................. 655
12.2 Register Descriptions ......................................................................................................... 656
12.2.1 Compare Match Timer Start Register (CMSTR) .................................................. 657
12.2.2 Compare Match Timer Control/Status Register (CMCSR) .................................. 658
12.2.3 Compare Match Counter (CMCNT) ..................................................................... 660
12.2.4 Compare Match Constant Register (CMCOR) ..................................................... 660
12.3 Operation ........................................................................................................................... 661
12.3.1 Interval Count Operation ...................................................................................... 661
12.3.2 CMCNT Count Timing......................................................................................... 661
12.4 Interrupts............................................................................................................................ 662
12.4.1 Interrupt Sources and DMA Transfer Requests .................................................... 662
12.4.2 Timing of Compare Match Flag Setting ............................................................... 662
12.4.3 Timing of Compare Match Flag Clearing............................................................. 663
12.5 Usage Notes ....................................................................................................................... 664
12.5.1 Conflict between Write and Compare-Match Processes of CMCNT ................... 664
12.5.2 Conflict between Word-Write and Count-Up Processes of CMCNT ................... 665
12.5.3 Conflict between Byte-Write and Count-Up Processes of CMCNT..................... 666
Section 13 Watchdog Timer (WDT)..................................................................667
13.1 Features.............................................................................................................................. 667
13.2 Input/Output Pin................................................................................................................. 669
13.3 Register Descriptions ......................................................................................................... 670
13.3.1 Watchdog Timer Counter (WTCNT).................................................................... 670
13.3.2 Watchdog Timer Control/Status Register (WTCSR)............................................ 671
13.3.3 Watchdog Reset Control/Status Register (WRCSR) ............................................ 673
13.3.4 Notes on Register Access...................................................................................... 674
13.4 WDT Usage ....................................................................................................................... 676
13.4.1 Canceling Software Standby Mode....................................................................... 676
13.4.2 Changing the Frequency ....................................................................................... 676
13.4.3 Using Watchdog Timer Mode............................................................................... 677
13.4.4 Using Interval Timer Mode .................................................................................. 679
13.5 Usage Notes ....................................................................................................................... 680
13.5.1 Timer Variation..................................................................................................... 680
13.5.2 Prohibition against Setting H'FF to WTCNT........................................................ 680
13.5.3 Interval Timer Overflow Flag ............................................................................... 680
13.5.4 System Reset by WDTOVF Signal....................................................................... 681
Rev. 2.00 Apr. 16, 2008 Page xvii of xxx
REJ09B0313-0200