SH7203 Datasheet, PDF (1221/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 USB 2.0 Host/Function Module (USB)
Table 23.15 Buffer Status Indicated by the BSTS Bit
ISEL or DIR
BSTS
0 (receiving direction) 0
0 (receiving direction) 1
1 (sending direction) 0
1 (sending direction) 1
Buffer Memory State
There is no received data, or data is being received.
Reading from the CPU is inhibited.
There is received data, or a zero-length packet has been
received.
Reading from the CPU is allowed.
However, because reading is not possible when a zero-
length packet is received, the buffer must be cleared.
The transmission has not been finished.
Writing to the CPU is inhibited.
The transmission has been finished.
Writing to the CPU is allowed.
Table 23.16 Buffer Status Indicated by the INBUFM Bit
IDIR
INBUFM
0 (receiving direction) Invalid
1 (sending direction) 0
1 (sending direction) 1
Buffer Memory State
Invalid
The transmission has been finished.
There is no waiting data to be sent.
There is data to be sent, because CPU (DMAC) has written
data to the buffer.
Rev. 2.00 Apr. 16, 2008 Page 1191 of 1652
REJ09B0313-0200