SH7203 Datasheet, PDF (169/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Exception Type
General illegal instruction
Integer division exception
FPU exception
Section 5 Exception Handling
Stack Status
SP
Start address of general
illegal instruction
SR
32 bits
32 bits
SP
Start address of relevant
integer division instruction
SR
32 bits
32 bits
SP
Address of instruction
after executed instruction
SR
32 bits
32 bits
Rev. 2.00 Apr. 16, 2008 Page 139 of 1652
REJ09B0313-0200