SH7203 Datasheet, PDF (1088/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 22 AND/NAND Flash Memory Controller (FLCTL)
22.3.4 Address Register (FLADR)
FLADR is a 32-bit readable/writable register that specifies an address to be output. The address of
the size specified by the command control register is output sequentially from ADR1 in byte units.
With the sector access address specification bit (ADRMD) in the command control register, it is
possible to specify whether the sector number set in the address data bits is converted into an
address to be output to the flash memory.
• ADRMD = 1
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADR4[7:0]
ADR3[7:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15
Initial value: 0
R/W: R/W
14
0
R/W
13
0
R/W
12 11
ADR2[7:0]
0
0
R/W R/W
10
0
R/W
9
0
R/W
8
0
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
3
ADR1[7:0]
0
0
R/W R/W
2
0
R/W
1
0
R/W
0
0
R/W
Initial
Bit
Bit Name Value R/W
31 to 24 ADR4[7:0] All 0 R/W
23 to 16 ADR3[7:0] All 0 R/W
15 to 8 ADR2[7:0] All 0 R/W
7 to 0 ADR1[7:0] All 0 R/W
Description
Fourth Address Data
Specify 4th data to be output to flash memory as an
address when ADRMD = 1.
Third Address Data
Specify 3rd data to be output to flash memory as an
address when ADRMD = 1.
Second Address Data
Specify 2nd data to be output to flash memory as an
address when ADRMD = 1.
First Address Data
Specify 1st data to be output to flash memory as an
address when ADRMD = 1.
Rev. 2.00 Apr. 16, 2008 Page 1058 of 1652
REJ09B0313-0200