SH7203 Datasheet, PDF (1600/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 31 Electrical Characteristics
31.4.8 SCIF Timing
Table 31.13 SCIF Timing
Conditions: VCC = PLLVCC = USBDVCC = 1.1 to 1.3 V, PVCC = USBDPVCC = 3.0 to 3.6 V,
AVCC = 3.0 to 3.6 V, USBAVCC = 1.1 to 1.3 V, USBAPVCC = 3.0 to 3.6 V,
VSS = PLLVSS = PVSS = AVSS = USBDVSS = USBAVSS = USBDPVSS =
USBAPVSS = 0 V, Ta = −20 to 85 °C
Item
Symbol Min.
Max.
Input clock cycle (clocked synchronous) t_Scyc
12
—
(asynchronous)
4
—
Input clock rise time
Input clock fall time
Input clock width
Transmit data delay time
(clocked synchronous)
t
—
SCKr
t_SCKf
—
t_SCKW
0.4
t_TXD
—
1.5
1.5
0.6
3 t_pcyc + 15
Receive data setup time
(clocked synchronous)
t_RXS
4 t_pcyc + 15 —
Receive data hold time
(clocked synchronous)
t
1 t + 15 —
RXH
pcyc
Note: t_pcyc indicates the peripheral clock (Pφ) cycle.
Unit
t_pcyc
t_pcyc
t
pcyc
t_pcyc
t_Scyc
ns
ns
ns
Figure
Figure 31.51
Figure 31.51
Figure 31.51
Figure 31.51
Figure 31.51
Figure 31.52
Figure 31.52
Figure 31.52
SCK
t_SCKW
t_SCKr
t_Scyc
t_SCKf
Figure 31.51 SCK Input Clock Timing
SCK
(input/output)
TxD
(data transmit)
RxD
(data receive)
t_Scyc
t_TXD
t_RXS t_RXH
Figure 31.52 SCIF Input/Output Timing in Clocked Synchronous Mode
Rev. 2.00 Apr. 16, 2008 Page 1570 of 1652
REJ09B0313-0200