SH7203 Datasheet, PDF (1572/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 31 Electrical Characteristics
CKIO
A25 to A0
CSn
RD/WR
RD
T1
Tw
t_AD1
t_CSD1 t_AS
t_CS
tRWD1
t_RSD
D31 to D0
Twx
T2B
Twb
T2B
t_AD2
tAD2
t_AD1
t_CSD1
tRDS3
t_RDH3
t_RWD1
t_RSD
t_RDS3
t_RDH3
WEn
BS
DACKn
TENDn*
WAIT
t_BSD
t_BSD
t_DACD
t_WTH
t_WTH
t_WTS
t_WTS
tDACD
Note: * The waveform for DACKn and TENDn is when active low is specified.
Figure 31.21 Burst ROM Read Cycle
(One Software Wait Cycle, One Asynchronous External Burst Wait Cycle, Two Burst)
Rev. 2.00 Apr. 16, 2008 Page 1542 of 1652
REJ09B0313-0200