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SH7203 Datasheet, PDF (1604/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
Section 31 Electrical Characteristics
31.4.10 IIC3 Timing
Table 31.15 IIC3 Timing
Conditions: VCC = PLLVCC = USBDVCC = 1.1 to 1.3 V, PVCC = USBDPVCC = 3.0 to 3.6 V,
AVCC = 3.0 to 3.6 V, USBAVCC = 1.1 to 1.3 V, USBAPVCC = 3.0 to 3.6 V,
VSS = PLLVSS = PVSS = AVSS = USBDVSS = USBAVSS = USBDPVSS =
USBAPVSS = 0 V, Ta = −20 to 85 °C
Item
Symbol Min.
SCL input cycle time
tSCL
SCL input high pulse width
tSCLH
SCL input low pulse width
tSCLL
SCL, SDA input rise time
tSr
SCL, SDA input fall time
tSf
SCL, SDA input spike pulse removal time*2 tSP
SDA input bus free time
tBUF
Start condition input hold time
tSTAH
Retransmit start condition input setup time tSTAS
Stop condition input setup time
tSTOS
Data input setup time
tSDAS
Data input hold time
tSDAH
SCL, SDA capacitive load
Cb
12
t *1
pcyc
+
600
3
t *1
pcyc
+
300
5
t *1
pcyc
+
300
—
—
—
5
3
3
3
1
t *1
pcyc
+
20
0
0
SCL, SDA output fall time*3
tSf
—
Notes: 1. tpcyc indicates the peripheral clock (Pφ) cycle.
2. Depends on the value of NF2CYC.
3. Indicates the I/O buffer characteristic.
Max.
—
—
—
300
300
1, 2
—
—
—
—
—
—
400
250
Unit Figure
ns Figure 31.57
ns
ns
ns
ns
t *1
pcyc
t *1
pcyc
t *1
pcyc
t *1
pcyc
t *1
pcyc
ns
ns
pF
ns
Rev. 2.00 Apr. 16, 2008 Page 1574 of 1652
REJ09B0313-0200