SH7203 Datasheet, PDF (1482/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 30 List of Registers
Module
Name Register Name
Abbreviation
Number
of Bits Address
Access
Size
RCAN- Timer Compare Match Register 0_0 TCMR0_0
TL1
Timer Compare Match Register 1_0 TCMR1_0
16
H'FFFF0098 16
16
H'FFFF009C 16
Timer Compare Match Register 2_0 TCMR2_0
16
H'FFFF00A0 16
Tx-Trigger Time Selection
Register_0
TTTSEL_0
16
H'FFFF00A4 16
Mailbox n Control 0_H_0
(n = 0 to 31)
MBn_CONTROL0_H_0 16
(n = 0 to 31)
H'FFFF0100
+ n×32
16, 32
Mailbox n Control 0_L_0
(n = 0 to 31)
MBn_CONTROL0_L_0 16
(n = 0 to 31)
H'FFFF0102 16
+ n×32
Mailbox n Local Acceptance Filter MBn_LAFM0_0
Mask 0_0 (n = 0 to 31)
(n = 0 to 31)
16
H'FFFF0104 16, 32
+ n×32
Mailbox n Local Acceptance Filter MBn_LAFM1_0
Mask 1_0 (n = 0 to 31)
(n = 0 to 31)
16
H'FFFF0106 16
+ n×32
Mailbox n Data 01_0 (n = 0 to 31) MBn_DATA_01_0
16
(n = 0 to 31)
H'FFFF0108
+ n×32
8, 16, 32
Mailbox n Data 23_0 (n = 0 to 31) MBn_DATA_23_0
16
(n = 0 to 31)
H'FFFF010A 8, 16
+ n×32
Mailbox n Data 45_0 (n = 0 to 31) MBn_DATA_45_0
16
(n = 0 to 31)
H'FFFF010C 8, 16, 32
+ n×32
Mailbox n Data 67_0 (n = 0 to 31) MBn_DATA_67_0
16
(n = 0 to 31)
H'FFFF010E 8, 16
+ n×32
Mailbox n Control 1_0 (n = 0 to 31) MBn_CONTROL1_0 16
(n = 0 to 31)
H'FFFF0110
+ n×32
8, 16
Mailbox n Time Stamp_0
(n = 0 to 15, 30, 31)
MBn_TIMESTAMP_0 16
(n = 0 to 15, 30, 31)
H'FFFF0112 + 16
n×32
Mailbox n Trigger Time_0
(n = 24 to 30)
MBn_TTT_0
(n = 24 to 30)
16
H'FFFF0114 16
+ n×32
Mailbox n TT Control_0
(n = 24 to 29)
MBn_TTCONTROL_0 16
(n = 24 to 29)
H'FFFF0116 16
+ n×32
Master Control Register_1
MCR_1
16
H'FFFF0800 16
General Status Register_1
GSR_1
16
H'FFFF0802 16
Bit Configuration Register 1_1
BCR1_1
16
H'FFFF0804 16
Bit Configuration Register 0_1
BCR0_1
16
H'FFFF0806 16
Interrupt Register_1
IRR_1
16
H'FFFF0808 16
Interrupt Mask Register_1
IMR_1
16
H'FFFF080A 16
Rev. 2.00 Apr. 16, 2008 Page 1452 of 1652
REJ09B0313-0200