SH7203 Datasheet, PDF (640/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.7.7 Contention between Buffer Register Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR
by the buffer operation is the data after write.
Figure 11.102 shows the timing in this case.
TGR write cycle
T1
T2
Pφ
Address
Write signal
Compare match
signal
Compare match
buffer signal
Buffer register
Buffer register
address
Buffer register write data
N
M
TGR
N
Figure 11.102 Contention between Buffer Register Write and Compare Match
Rev. 2.00 Apr. 16, 2008 Page 610 of 1652
REJ09B0313-0200