SH7203 Datasheet, PDF (770/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 15 Serial Communication Interface with FIFO (SCIF)
Table 15.4 Bit Rates and SCBRR Settings (Asynchronous Mode, BGDM = 0, ABCS = 0) (3)
Bit Rate
(bit/s) _n
110
3
150
3
300
2
600
2
1200 1
2400 1
4800 0
9600 0
19200 0
31250 0
38400 0
20
Error
N (%) n
88 −0.25 3
64 0.16 3
129 0.16 2
64 0.16 2
129 0.16 1
64 0.16 1
129 0.16 0
64 0.16 0
32 −1.36 0
19 0.00 0
15 1.73 0
24
N
106
77
155
77
155
77
155
77
38
23
19
Pφ (MHz)
Error
(%) n
−0.44 3
0.16 3
0.16 2
0.16 2
0.16 1
0.16 1
0.16 0
0.16 0
0.16 0
0.00 0
−2.34 0
24.576
Error
N
(%) n
108 0.08 3
79 0.00 3
159 0.00 2
79 0.00 2
159 0.00 1
79 0.00 1
159 0.00 0
79 0.00 0
39 0.00 0
24 −1.70 0
19 0.10 0
28.7
Error
N (%)
126 0.31
92 0.46
186 −0.08
92 0.46
186 −0.08
92 0.46
186 −0.08
92 0.46
46 −0.61
28 −1.03
22 1.55
Rev. 2.00 Apr. 16, 2008 Page 740 of 1652
REJ09B0313-0200