SH7203 Datasheet, PDF (1151/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Bit
Bit Name
11 to 6 ⎯
5
SIGNE
4
SACKE
3
⎯
2
BRDYM
1, 0
⎯
Section 23 USB 2.0 Host/Function Module (USB)
Initial
Value R/W Description
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
0
R/W Setup Transaction Error Interrupt Enable
0: Interrupt output disabled
1: Interrupt output enabled
0
R/W Setup Transaction Normal Response Interrupt
Enable
0: Interrupt output disabled
1: Interrupt output enabled
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
0
R/W BRDY Interrupt Status Clear Timing Control for Each
Pipe
0: Software clears the status.
1: This module clears the status by reading from or
writing to the FIFO buffer.
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 Apr. 16, 2008 Page 1121 of 1652
REJ09B0313-0200