SH7203 Datasheet, PDF (1153/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name
Value R/W Description
1
PIPE1BRDYE 0
R/W BRDY interrupt Enable for PIPE1
0: Interrupt output disabled
1: Interrupt output enabled
0
PIPE0BRDYE 0
R/W BRDY interrupt Enable for PIPE0
0: Interrupt output disabled
1: Interrupt output enabled
Note: If an interrupt is enabled/disabled after the interrupt status was cleared, an interval of 80 ns
or more is required.
23.3.14 NRDY Interrupt Enable Register (NRDYENB)
NRDYENB is a register that enables NRDY interrupts for each pipe.
This register is initialized by a power-on reset or a software reset.
Bit: 15 14 13 12 11 10 9
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
8
7
6
5
4
3
2
1
0
-
PIPE7 PIPE6 PIPE5 PIPE4 PIPE3 PIPE2 PIPE1 PIPE0
NRDYE NRDYE NRDYE NRDYE NRDYE NRDYE NRDYE NRDYE
0
0
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name
Value R/W Description
15 to 8 ⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
7
PIPE7NRDYE 0
R/W NRDY Interrupt Enable for PIPE7
0: Interrupt output disabled
1: Interrupt output enabled
6
PIPE6NRDYE 0
R/W NRDY Interrupt Enable for PIPE6
0: Interrupt output disabled
1: Interrupt output enabled
Rev. 2.00 Apr. 16, 2008 Page 1123 of 1652
REJ09B0313-0200