SH7203 Datasheet, PDF (1202/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 USB 2.0 Host/Function Module (USB)
(1) Zero-length packet reception or data packet reception when BFRE = 0
(short packet reception/transaction counter completion/buffer full)
USB bus
Token packet
Zero-length packet/
short data packet/
data packet (full)
(transaction count)
ACK handshake
BRDY
interrupt
A BRDY interrupt is generated
because reading from the buffer
is enabled.
(2) Data packet reception when BFRE = 1 (short packet reception/transaction counter completion)
USB bus
Token packet
Short data packet/
data packet
(transaction count)
ACK handshake
Buffer read
BRDY
interrupt
(3) Packet transmission
USB bus
Buffer write
A BRDY interrupt is generated
because the transfer has ended
Token packet
Data packet
ACK handshake
BRDY
interrupt
A BRDY interrupt is generated
because writing to the buffer is enabled.
Figure 23.3 Timing at which a BRDY Interrupt is Generated
Table 23.13 Conditions for Clearing the BRDY Bit
BRDYM
0
1
Conditions for Clearing the BRDY Bit
When software clears all of the bits in BRDYSTS, this module clears the BRDY
bit in INSTS0.
When the BTST bits for all pipes are cleared to 0, this module clears the BRDY
bit in INTSTS0.
Rev. 2.00 Apr. 16, 2008 Page 1172 of 1652
REJ09B0313-0200