SH7203 Datasheet, PDF (1321/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

24.6 Usage Notes
Section 24 LCD Controller (LCDC)
24.6.1 Procedure for Halting Access to Display Data Storage VRAM (Synchronous
DRAM in Area 3)
Follow the procedure below to halt access to VRAM for storing display data (synchronous DRAM
in area 3).
• Procedure for Halting Access to Display Data Storage VRAM:
1. Confirm that the LPS1 and LPS0 bits in LDPMMR are currently set to 1.
2. Clear the DON bit in LDCNTR to 0 (display-off mode).
3. Confirm that the LPS1 and LPS0 bits in LDPMMR have changed to 0.
4. Wait for the display time for a single frame to elapse.
This halting procedure is required before selecting self-refreshing for the display data storage
VRAM (synchronous DRAM in area 3) or making a transition to standby mode or module standby
mode.
Rev. 2.00 Apr. 16, 2008 Page 1291 of 1652
REJ09B0313-0200