SH7203 Datasheet, PDF (1189/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 USB 2.0 Host/Function Module (USB)
23.3.36 PIPEn Control Registers (PIPEnCTR) (n = 1 to 7)
PIPEnCTR is a register that is used to confirm the buffer memory status for the corresponding
pipe, change and confirm the data PID sequence bit, determine whether the auto response mode is
set, determine whether the auto buffer clear mode is set, and set a response PID. This register can
be set regardless of the pipe selection in PIPESEL.
This register is initialized by a power-on reset or a software reset. PID[1:0] are initialized by a
USB bus reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
BSTS INBUFM -
-
-
AT
REPM
ACLRM SQCLR SQSET SQMON
-
-
-
-
PID[1:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R R/W R/W R/W*¹ R/W*¹ R
R
R
R
R R/W R/W
Bit
Bit Name
15
BSTS
14
INBUFM
13 to 11 ⎯
10
ATREPM
Initial
Value R/W
0
R
0
R
All 0 R
0
R/W
Description
Buffer Status
0: Buffer access is disabled
1: Buffer access is enabled
The direction of buffer access, writing or reading,
depends on setting of the DIR bit in PIPECFG. For
details, see section 23.4, Operation.
IN Buffer Monitor
This bit is valid when the corresponding pipe is set to
the transmitting direction.
0: There is no data to be transmitted in the buffer
memory
1: There is data to be transmitted in the buffer
memory
Note: This bit is valid for PIPE1 to PIPE5.
Reserved
These bits are always read as 0. The write value
should always be 0.
Auto Response Mode
0: Normal mode
1: Auto response mode
Note: This bit is valid for PIPE1 to PIPE5.
Rev. 2.00 Apr. 16, 2008 Page 1159 of 1652
REJ09B0313-0200