SH7203 Datasheet, PDF (1168/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 USB 2.0 Host/Function Module (USB)
23.3.21 Frame Number Register (FRMNUM)
FRMNUM is a register that determines the source of isochronous error notification, selects SOFR
interrupt operating mode, and indicates the frame number.
This register is initialized by a power-on reset or a software reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
OVRN CRCE -
- SOFRM
FRNM[10:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W*¹ R/W*¹ R
R R/W R
R
R
R
R
R
R
R
R
R
R
Bit
Bit Name
15
OVRN
14
CRCE
13, 12 ⎯
Initial
Value
0
0
All 0
R/W
R/W*¹
R/W*¹
R
Description
Overrun/Underrun*²
0: No error
1: An error occurred
Indicates that a data buffer error is the source of
error notification with the NRDY interrupt for the pipe
in which isochronous transfer is being performed.
For details, see tables 23.8 and 23.9.
Receive Data Error*²
0: No error
1: An error occurred
Indicates that the source of error notification with the
NRDY interrupt for the pipe in which isochronous
transfer is being performed is a packet error.
For details, see tables 23.8 and 23.9.
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 Apr. 16, 2008 Page 1138 of 1652
REJ09B0313-0200