SH7203 Datasheet, PDF (1287/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 LCD Controller (LCDC)
Initial
Bit
Bit Name Value R/W Description
0
DON
0
R/W Display On
Specifies the start and stop of the LCDC display
operation.
The control sequence state can be checked by
referencing the LPS[1:0] of LDPMMR.
0: Display-off mode: LCDC is stopped
1: Display-on mode: LCDC operates
Notes: 1. Write H'0011 to LDCNTR to start display output and H'0000 to end display output. Data
other than H'0011 and H'0000 must not be written here.
2. Setting bit DON2 to 1 makes the contents of the palette RAM undefined. Before writing
to the palette RAM, set bit DON2 to 1.
3. After writing to LDCNTR, it takes some time for the display to actually start or stop.
Thus, to access another register of the LCDC after writing to LDCNTR, dummy-read
LDCNTR once beforehand.
24.3.20 LCDC User Specified Interrupt Control Register (LDUINTR)
LDUINTR sets whether the user specified interrupt is generated, and indicates its processing state.
This interrupt is generated at the time when image data which is set by the line number register
(LDUINTLNR) in LCDC is read from VRAM.
This LCDC issues the interrupts (LCDCI): user specified interrupt by this register, memory access
interrupt by the LCDC interrupt control register (LDINTR), and OR of Vsync interrupt output.
This register and LCDC interrupt control register (LDINTR) settings affect the interrupt operation
independently.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
- UINTEN -
-
-
-
-
-
- UNITS
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R R/W R
R
R
R
R
R
R R/W
Bit
Bit Name
15 to 9 ⎯
Initial
Value R/W
All 0 R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 2.00 Apr. 16, 2008 Page 1257 of 1652
REJ09B0313-0200