SH7203 Datasheet, PDF (821/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Initial
Bit
Bit Name Value R/W
2 to 0 CKS[2:0] 000
R/W
Section 16 Synchronous Serial Communication Unit (SSU)
Description
Transfer Clock Rate Select
Select the transfer clock rate (prescaler division rate)
when an internal clock is selected.
000: Reserved
001: Pφ/4
010: Pφ/8
011: Pφ/16
100: Pφ/32
101: Pφ/64
110: Pφ/128
111: Pφ/256
16.3.4 SS Enable Register (SSER)
SSER enables transmission/reception and interrupt requests.
Bit: 7
6
5
TE RE
-
Initial value: 0
0
0
R/W: R/W R/W R
4
3
2
1
0
- TEIE TIE RIE CEIE
0
0
0
0
0
R R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W
7
TE
0
R/W
6
RE
0
R/W
5, 4 ⎯
All 0
R
3
TEIE
0
R/W
Description
Transmit Enable
When this bit is set to 1, transmission is enabled.
Receive Enable
When this bit is set to 1, reception is enabled.
Reserved
These bits are always read as 0. The write value should
always be 0.
Transmit End Interrupt Enable
When this bit is set to 1, an SSTXI interrupt request
caused by transmit end is enabled.
Rev. 2.00 Apr. 16, 2008 Page 791 of 1652
REJ09B0313-0200