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SH7203 Datasheet, PDF (450/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
Section 10 Direct Memory Access Controller (DMAC)
CHCR DMARS DMA Transfer
Request
RS[3:0] MID RID Source
Transfer
DMA Transfer Request Signal Source
Transfer Bus
Destination Mode
1000 100010 01 SCIF_2
TXI2 (transmission FIFO data Any
transmission empty)
SCFTDR_2 Cycle
steal
10 SCIF_2
reception
RXI2 (reception FIFO data full) SCFRDR_2 Any
100011 01 SCIF_3
TXI3 (transmission FIFO data Any
transmission empty)
SCFTDR_3
10 SCIF_3
reception
RXI3 (reception FIFO data full) SCFRDR_3 Any
101100 11 A/D converter ADI (A/D conversion end)
ADDR
Any
Cycle
steal
101110 11 FLCTL data part Transmission FIFO data empty
transmission
FLCTL data part Reception FIFO data full
reception
101111 11
FLCTL control
code part
transmission
Transmission FIFO data empty
FLCTL control
code part
reception
Reception FIFO data full
111000 11 MTU2_0
TGI0A (input capture/compare
match)
111001 11 MTU2_1
TGI1A (input capture/compare
match)
111010 11 MTU2_2
TGI2A (input capture/compare
match)
111011 11 MTU2_3
TGI3A (input capture/compare
match)
111100 11 MTU2_4
TGI4A (input capture/compare
match)
111110 11 CMT_0
CMI0 (compare match)
111111 11 CMT_1
CMI1 (compare match)
Any
FLDTFIFO Cycle
steal
FLDTFIFO Any
Any
FLECFIFO
FLECFIFO Any
Any
Any
Cycle
steal or
Any
Any
burst
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Rev. 2.00 Apr. 16, 2008 Page 420 of 1652
REJ09B0313-0200