SH7203 Datasheet, PDF (1154/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name
Value R/W Description
5
PIPE5NRDYE 0
R/W NRDY Interrupt Enable for PIPE5
0: Interrupt output disabled
1: Interrupt output enabled
4
PIPE4NRDYE 0
R/W NRDY Interrupt Enable for PIPE4
0: Interrupt output disabled
1: Interrupt output enabled
3
PIPE3NRDYE 0
R/W NRDY Interrupt Enable for PIPE3
0: Interrupt output disabled
1: Interrupt output enabled
2
PIPE2NRDYE 0
R/W NRDY Interrupt Enable for PIPE2
0: Interrupt output disabled
1: Interrupt output enabled
1
PIPE1NRDYE 0
R/W NRDY Interrupt Enable for PIPE1
0: Interrupt output disabled
1: Interrupt output enabled
0
PIPE0NRDYE 0
R/W NRDY Interrupt Enable for PIPE0
0: Interrupt output disabled
1: Interrupt output enabled
Note: If an interrupt is enabled/disabled after the interrupt status was cleared, an interval of 80 ns
or more is required.
Rev. 2.00 Apr. 16, 2008 Page 1124 of 1652
REJ09B0313-0200