SH7203 Datasheet, PDF (34/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 1 Overview
Items
Specification
Bus state controller
(BSC)
• Address space divided into eight areas (0 to 7), each a maximum of 64
Mbytes
• The following features settable for each area independently
⎯ Bus size (8, 16, or 32 bits): Available sizes depend on the area.
⎯ Number of access wait cycles (different wait cycles can be
specified for read and write access cycles in some areas)
⎯ Idle wait cycle insertion (between same area access cycles or
different area access cycles)
⎯ Specifying the memory to be connected to each area enables
direct connection to SRAM, SRAM with byte selection, SDRAM,
and burst ROM (clocked synchronous or asynchronous). The
address/data multiplexed I/O (MPX) interface and burst MPX-I/O
interface are also available.
⎯ PCMCIA interface
⎯ Outputs a chip select signal (CS0 to CS7) according to the target
area (CS assert or negate timing can be selected by software)
• SDRAM refresh
Auto refresh or self refresh mode selectable
• SDRAM burst access
Direct memory access • Eight channels; external request available for four of them
controller (DMAC)
• Can be activated by on-chip peripheral modules
• Burst mode and cycle steal mode
• Intermittent mode available (16 and 64 cycles supported)
• Transfer information can be automatically reloaded
Clock pulse generator • Clock mode: Input clock can be selected from external input (EXTAL,
(CPG)
CKIO, or USB_X1) or crystal resonator
• Input clock can be multiplied by 16 (max.) by the internal PLL circuit
• Three types of clocks generated:
⎯ CPU clock: Maximum 200 MHz
⎯ Bus clock: Maximum 66 MHz
⎯ Peripheral clock: Maximum 33 MHz
Watchdog timer
(WDT)
• On-chip one-channel watchdog timer
• A counter overflow can reset the LSI
Rev. 2.00 Apr. 16, 2008 Page 4 of 1652
REJ09B0313-0200