SH7203 Datasheet, PDF (696/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 12 Compare Match Timer (CMT)
12.5.3 Conflict between Byte-Write and Count-Up Processes of CMCNT
Even when the count-up occurs in the T2 cycle while writing to CMCNT in bytes, the writing has
priority over the count-up. In this case, the count-up is not performed. The byte data on the other
side, which is not written to, is also not counted and the previous contents are retained.
Figure 12.7 shows the timing when the count-up occurs in the T2 cycle while writing to
CMCNTH in bytes.
Peripheral clock
(Pφ)
Address signal
Internal write signal
CMCNT count-up
enable signal
CMCNTH
CMCSR write cycle
T1
T2
CMCNTH
N
M
CMCNTL
X
X
Figure 12.7 Conflict between Byte-Write and Count-Up Processes of CMCNT
Rev. 2.00 Apr. 16, 2008 Page 666 of 1652
REJ09B0313-0200