SH7203 Datasheet, PDF (1563/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 31 Electrical Characteristics
Bφ = 66.66 MHz*¹*²
Item
Symbol Min.
Max.
Unit Figure
RAS delay time 1
RAS delay time 2
CAS delay time 1
CAS delay time 2
DQM delay time 1
t_RASD1
t_RASD2
t
CASD1
t
CASD2
t_DQMD1
1
1/2t_cyc
1
1/2t
cyc
1
13
ns
1/2t_cyc + 13 ns
13
ns
1/2t + 13 ns
cyc
13
ns
Figures 31.22 to
31.38
Figures 31.39, 31.40
Figures 31.22 to
31.38
Figures 31.39, 31.40
Figures 31.22 to
31.35
DQM delay time 2
CKE delay time 1
CKE delay time 2
AH delay time
Multiplexed address delay
time
t
DQMD2
t
CKED1
t_CKED2
t_AHD
t_MAD
1/2t
cyc
1
1/2t_cyc
1/2t_cyc
—
1/2t + 13 ns
cyc
13
ns
1/2t_cyc + 13 ns
1/2t_cyc + 13 ns
13
ns
Figures 31.39, 31.40
Figure 31.37
Figure 31.40
Figure 31.17
Figure 31.17
Multiplexed address hold time t_MAH
Address setup time relative to t_AWH
AH
1
—
1/2t_cyc - 2 —
ns
Figure 31.17
ns
Figure 31.17
DACK, TEND delay time
t_DACD
Refer to DMAC timing ns
Figures 31.13 to
31.35, 31.39, 31.41
to 31.44
FRAME delay time
t
0
13
ns
Figure 31.18
FMD
ICIORD delay time
t_ICRSD
—
1/2t_cyc + 13 ns
Figures 31.43, 31.44
ICIOWR delay time
t_ICWSD
—
1/2t_cyc + 13 ns
Figures 31.43, 31.44
Notes: 1. The maximum value (fmax) of Bφ (external bus clock) depends on the number of wait
cycles and the system configuration of your board.
2. 1/2 t_cyc indicated in minimum and maximum values for the item of delay, setup, and hold
times represents a half cycle from the rising edge with a clock. That is, 1/2 t_cyc describes
a reference of the falling edge with a clock.
Rev. 2.00 Apr. 16, 2008 Page 1533 of 1652
REJ09B0313-0200