SH7203 Datasheet, PDF (1462/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 29 User Debugging Interface (H-UDI)
Initial
Bit
Bit Name Value
R/W Description
1
⎯
0
R
Reserved
This bit is always read as 0.
0
⎯
1
R
Reserved
This bit is always read as 1.
Table 29.3 H-UDI Commands
Bits 15 to 8
TI7 TI6 TI5 TI4 TI3 TI2 TI1 TI0 Description
0
1
1
0
—
—
—
—
H-UDI reset negate
0
1
1
1
—
—
—
—
H-UDI reset assert
1
0
0
1
1
1
0
0
TDO change timing switch
1
0
1
1
—
—
—
—
H-UDI interrupt
1
1
1
1
—
—
—
—
BYPASS mode
Other than above
Reserved
Rev. 2.00 Apr. 16, 2008 Page 1432 of 1652
REJ09B0313-0200