SH7203 Datasheet, PDF (711/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 13 Watchdog Timer (WDT)
13.5.4 System Reset by WDTOVF Signal
If the WDTOVF signal is input to the RES pin of this LSI, this LSI cannot be initialized correctly.
Avoid input of the WDTOVF signal to the RES pin of this LSI through glue logic circuits. To
reset the entire system with the WDTOVF signal, use the circuit shown in figure 13.6.
Reset input
(Low active)
Reset signal to
entire system
(Low active)
RES
WDTOVF
Figure 13.6 Example of System Reset Circuit Using WDTOVF Signal
13.5.5 Manual Reset in Watchdog Timer Mode
When a manual reset occurs in watchdog timer mode, the bus cycle is continued. If a manual reset
occurs while the bus is released or during DMAC burst transfer, manual reset exception handling
will be pended until the CPU acquires the bus mastership.
Rev. 2.00 Apr. 16, 2008 Page 681 of 1652
REJ09B0313-0200