SH7203 Datasheet, PDF (636/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.7 Usage Notes
11.7.1 Module Standby Mode Setting
MTU2 operation can be disabled or enabled using the standby control register. The initial setting
is for MTU2 operation to be halted. Register access is enabled by clearing module standby mode.
For details, refer to section 28, Power-Down Modes.
11.7.2 Input Clock Restrictions
The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at
least 2.5 states in the case of both-edge detection. The MTU2 will not operate properly at narrower
pulse widths.
In phase counting mode, the phase difference and overlap between the two input clocks must be at
least 1.5 states, and the pulse width must be at least 2.5 states. Figure 11.98 shows the input clock
conditions in phase counting mode.
TCLKA
(TCLKC)
TCLKB
(TCLKD)
Phase
Phase
differ-
differ-
Overlap ence Overlap ence
Pulse width
Pulse width
Pulse width
Pulse width
Notes: Phase difference and overlap : 1.5 states or more
Pulse width
: 2.5 states or more
Figure 11.98 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
Rev. 2.00 Apr. 16, 2008 Page 606 of 1652
REJ09B0313-0200