SH7203 Datasheet, PDF (228/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 7 User Break Controller (UBC)
Initial
Bit
Bit Name Value R/W Description
9, 8
CP[1:0]
00
R/W I-Bus Bus Select
Select the bus when the bus cycle of the break
condition is the I bus cycle. However, when the C bus
cycle is selected, this bit is invalidated (only the CPU
cycle).
00: Condition comparison is not performed
01: Break condition is the internal CPU bus
10: Break condition is the internal DMA bus
11: Break condition is the internal CPU bus
7, 6
CD[1:0]
00
R/W C Bus Cycle/I Bus Cycle Select
Select the C bus cycle or I bus cycle as the bus cycle
of the break condition.
00: Condition comparison is not performed
01: Break condition is the C bus (F bus or M bus) cycle
10: Break condition is the I bus cycle
11: Break condition is the C bus (F bus or M bus) cycle
5, 4
ID[1:0]
00
R/W Instruction Fetch/Data Access Select
Select the instruction fetch cycle or data access cycle
as the bus cycle of the break condition. If the
instruction fetch cycle is selected, select the C bus
cycle.
00: Condition comparison is not performed
01: Break condition is the instruction fetch cycle
10: Break condition is the data access cycle
11: Break condition is the instruction fetch cycle or
data access cycle
3, 2
RW[1:0]
00
R/W Read/Write Select
Select the read cycle or write cycle as the bus cycle of
the break condition.
00: Condition comparison is not performed
01: Break condition is the read cycle
10: Break condition is the write cycle
11: Break condition is the read cycle or write cycle
Rev. 2.00 Apr. 16, 2008 Page 198 of 1652
REJ09B0313-0200